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  Dual Intel Pentium 4 Xeon Preview 
  May 11, 2001, 10:00am EDT 
 

i860 Chipset Details


By: Sander Sassen

Architecturally, the Xeon DP shares all of its core basics with the Pentium 4 processor. Centered on the NetBurst micro-architecture, the Xeon DP naturally has inherited the Pentium 4ís 20-stage pipeline. Similarly, the execution trace cache, capable of storing up to 12,000 micro-ops has also been passed down. Since the Xeon, like the Pentium 4, will suffer from a lower average number of executed instructions per second, Intel has implemented the same 'double-pumped' Arithmetic Logic Units. Further minimizing the penalty for the deep pipeline is an improved branch prediction algorithm. SSE2 rounds out the package, demonstrating significant speed improvements in multimedia-based applications optimized to take advantage of the technology.

Pentium 4 Xeon Top


Fig 1. The Intel Pentium 4 Xeon CPU, notice the components mounted on the PCB for power decoupling and filtering.

The first major departure from the Pentium 4 comes in the supporting chipset. Whereas the i850 has been standard fare for P4 systems, multi-processing requires logic far more complex than that of a uni-processor system, giving way to the i860 chipset. The memory controller hub (MCH) component facilitates communication between the processors, graphics controller, memory, and PCI64 controller. Like the i850 before it, the i860 also incorporates a 100MHz system bus, quad pumped for the equivalent of 3.2GB/s of bandwidth.

It has been shown that the Pentium 4 is sensitive to available bandwidth, so it will be particularly interesting to see how a dual Xeon system fares with its two processors sharing the theoretical 3.2GB/s of bandwidth. Memory bandwidth has been matched at 3.2GB/s compliments of the dual RDRAM channels. Since the Xeon is targeted towards high-end workstations, the memory ceiling has been raised to 4GB, using two memory repeater hubs.

As previously mentioned, PCI64 support has been added for 64-bit devices that can take advantage of the 800MB/s of bandwidth provided. Each 64-bit channel is linked directly to the MCH, circumventing the congested PCI bus that is extended from the I/O Controller Hub (ICH2). With up to 266MB/s of bandwidth to the MCH, the ICH2 is responsible for the dual ATA/100 channels, integrated audio and LAN, USB, and 32-bit PCI interface.



1. Introduction
2. i860 Chipset Details
3. Pentium 4 Xeon Details

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