Since the Xeon is running at such high clock speeds, extra pins are needed to account for routing and electromagnetic compatibility, keeping the Xeon stable. Rather than utilize the Socket 423 interface, Intel has steered the Xeon DP over to a Socket 603 interface, with pin-outs much closer together than anything available today.
Fig 2. The Intel Pentium 4 Xeon CPU, notice the very small form factor of the socket-603 and the large number of pins concentrated in a small area.
So where is the Xeon DP headed? The benefit to the Xeon of old (Pentium II Xeon) was eclipsed when the mainstream Pentium III obtained an on-die level two cache. Similarly, all of the architectural features found on the Xeon can already be had with the Pentium 4. Rather, the Xeon DP will show an advantage in multi-threaded applications that take advantage of more than one processor. Moreover, when versions of the processor are released with larger caches, the result of the two processors sharing 3.2GB/s of bandwidth should become less apparent as more data can be retrieved from the much faster cache. Memory limitations have all but been eliminated thanks to the 4GB limit of the i860 chipset. Finally, PCI64 helps leverage the Xeon at the upper echelon of workstation systems that utilize SCSI and gigabit Ethernet.
Later in the year, we expect Intel to unveil a version of the Xeon capable to scaling past dual processing, into four and eight-way servers. Once this occurs, Intel will be set to outfit not only high-end workstations, but also entry-level back-end servers with the fastest processors in their IA-32 lineup.
Stay tuned, as a we're currently working on a full review of the Xeon DP which can be expected as soon as it is officially launched.