Despite Moore's Law the 1GHz mark had seemed a tough hurdle to overcome. Having a processor run at 1 GHz at room temperature requires more than just a die-shrink, a big and efficient heatsink or another revision of the processor's microcode; it is really stretching the limits of CPU architecture. In the case of the Pentium 4 a new architecture was the only route to increasing the clockspeed, as the aging P6 core had already long since exceeded its design limits.
However, having a processor running at 1+ GHz is useless if it is sitting idle and waiting for data to process. Therefore we have to make sure that the rest of the system is capable of feeding enough data to keep it running efficiently. One of the biggest bottlenecks is the memory subsystem responsible for data storage and retrieval. A processor capable of sustaining a, for example, 2 GB/s bandwidth to the main memory will be severely bottlenecked by a memory bandwidth of only 800 MB/s.
Most code is executed from main memory, and approximately 80% of a processor's cycles are devoted to manipulating this data. With current processor and memory architectures, a 1+ GHz processor demands a memory bus actually capable of that bandwidth. Significant performance benefits await adequate chipsets.
Upon looking at upcoming DDR and current RDRAM and SDRAM chipsets, one thing is very obvious; they're all bottlenecked by the system bus connecting the CPU to the motherboard's chipset. With all current chipset implementations, except the Intel 850, the upcoming i860 and AMD's AMD760 DDR chipset, the system bus operates at either 100 or 133 MHz, yielding a theoretical maximum bandwidth of just over 1 GB/s. Even if a memory architecture is capable of delivering 1.6 or 2.1GB/s of sustained throughput, we're never going to see a substantial improvement in performance because of the system bus bottleneck.
So in order for the Pentium 4, and frankly any other 1+ GHz CPU, to run efficiently, the chipset has to remove bottlenecks between the CPU and main memory. Only removing them in combination with increased clockspeed will effect substantial improvement in performance.
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