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  Intel's Pentium 4, a closer look 
  May 17, 2001, 12:00pm EDT 


By: Sander Sassen

The Pentium 4 is the first offspring of a new Micro-Architecture, an architecture that has the potential to take the performance crown if Intel can motivate developers to start using the optimized compilers and SSE2. The Pentium 4's NetBurst architecture is designed for low latency and high throughout, as the memory throughput clearly shows. However, the long pipeline does put the brakes on performance quite a bit, but is a necessity if the Pentium 4 is to have enough clockspeed scalability. With the current 0.18micron process we'll soon see 1.8 and 2 GHz CPUs that will put the Pentium 4's performance in a whole different light.

If the Pentium 4 had been released a few months ago, as was originally planned, things would have looked different. It would have had to compete with sub- to 1GHz Intel and AMD parts and it would simply have had a much bigger impact. With AMD's 760 DDR chipset and the 266 MHz FSB Athlons also available it faces much stiffer competition. And with the Athlon 4 to be released soon, it'll be interesting to see how well the Pentium 4 will stack up.

A requirement for the Pentium 4's success will be the availability of an SDRAM and DDR SDRAM chipset, or a further reduction in RDRAM prices and generally better availability, to compete with AMD's offerings. That in combination with better software support for SSE2 and optimized compilers to support those features in games and applications. Upon looking at the performance delta offered by Nvidia’s latest Detonator drivers and the updates for Photoshop offered by Adobe it looks like the Pentium 4 has quite some headroom left if these SSE2 instructions are correctly implemented and used. If Intel can get the clockspeed ramped up quickly and make sure compiler and SSE2 support is implemented properly, Intel might soon be able to put the 'World's Fastest x86 CPU' sticker back on.

Sander Sassen.

1. Introduction
2. Clockspeed and Bandwidth
3. Pipelining and Performance
4. Pipelining and Performance Cont.
5. Branch Prediction
6. Branch Prediction Cont.
7. SSE2 and Misc. Features
8. Conclusion

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