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  Intel's Pentium 4, a closer look 
  May 17, 2001, 12:00pm EDT 
 

Introduction


By: Sander Sassen

Intel's Pentium 4, formerly known by its codename, Willamette, is the latest member of the IA-32 family of Intel CPUs, and the first successor to the Intel P6 core. The Intel P6s started off with the Intel Pentium Pro a few years ago, laying the foundation of a whole family of Intel CPUs.

The Pentium Pro came in a wide variety of clockspeeds and L2-cache configurations, with external L2-cache running at full clockspeed. It was initially targeted at the server market but offered a very competitive solution for the workstation market too, due to its powerful FPU. Its well-known successor, the Intel Pentium II, was the logical follow-up, using much of the Pentium Pro's design and FPU; it added MMX technology to the P6 CPU core and an external L2-cache running at half CPU clockspeed. The Pentium III added a number of enhancements, such as Streaming SIMD Extensions (SSE) for enhanced floating point and 3D application performance and the Intel Processor Serial Number, a feature that enables a CPU to be uniquely identified.

The Intel Pentium III Coppermine heralded the return of the L2-cache running at full clock speed, much as in the original Pentium Pro, as well as a die-shrink to 0.18micron. While the Intel Pentium Pro L2-cache was mounted inside the CPU package, on the Coppermine the L2-cache is actually on-die, reducing cost and improving cache latency and throughput.

The Intel Pentium 4 CPU is based on a new 32-bit micro-architecture, featuring on-die L2-cache, a very deep pipeline and SSE2, a further development of SSE as featured on the Pentium III, plus other enhancements that allow the Pentium IV to operate at significantly higher clock speeds and deliver prospective performance levels significantly higher than the Pentium II/III.

Pentium 4


Fig 1. The Pentium 4 CPU, manufactured in Intelís .18-micron aluminum process.



1. Introduction
2. Clockspeed and Bandwidth
3. Pipelining and Performance
4. Pipelining and Performance Cont.
5. Branch Prediction
6. Branch Prediction Cont.
7. SSE2 and Misc. Features
8. Conclusion

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