The ATA standard as we know it today has been in place for some years, and in its current form since the launch of Intelís 440LX/BX core logic, which featured the first native ATA-33 (UDMA Mode 2) support. Since then, subsequent ATA standards have merely increased the rate at which data can be moved through the bus in logical steps. In other words, theyíve been very evolutionary steps. The next step was the move to ATA-66 (UDMA Mode 4), which occurred en masse when Intel introduced itís 810 and 820 chipsets in late 1998. Capable of transferring at over 66MB/s, ATA-66 doubled the data bandwidth offered by ATA-33. Not surprisingly, the next evolutionary step, ATA-100 (UDMA Mode 5), was introduced just over a year ago, and bumped the available bandwidth up to 100MB/s. ATA-133 (UDMA Mode 6) will now increase that further to 133MB/s. Each new standard has been fully backward-compatible.
Each of the aforementioned ATA specifications have all been based on a parallel bus design. Bandwidth is effectively a product of two factors; bus width, and bus speed. Unfortunately, electrically speaking, itís very difficult to design a bus that is both high-speed and wide, so usually width is compromised in favor of speed, or visa versa. In a parallel-type design, bus width is increased at the expense of speed. Large data packets are sent wholly, but at slower speeds. Conversely, in a serial design, bus width is sacrificed in favor of speed. Packets are broken down, and sent piece by piece, but at a much faster rate. Neither design is universally better; both have advantages and disadvantages.
There has been somewhat of a push in recent years to pursue a serial ATA bus instead of the current parallel design. Many see the parallel ATA standard as a limitation, and would seek to promote a higher speed serial design (in addition, serial bus designs have other advantages, such as lower pin counts, and can therefore accommodate longer, thinner cables, and more devices). Opponents argue that the drives are the limiting factor in performance, not the interface, and thus that altering the ATA standard is not necessary at this point.
A year or two ago, it was predicted that Serial ATA would have replaced the current parallel ATA standard by now, and that ATA-100 would likely have been the last parallel ATA standard. Clearly that hasnít taken place, and in fact, news of Serial ATA seems to have become sparse in recent months. Maxtor, along with Seagate and Intel, has been a major proponent of Serial ATA from the start, and even it seems to be quiet lately. In any event, given the limitations of the PCI bus (which weíll talk more about later), it seems likely that ATA-133 will likely be the last evolutionary standard introduced, before more radical changes are required.
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