http://media.hardwareanalysis.com/articles/small/10428.gif" alt="Hardware Analysis - 533 MHz FSB" border=0>
Here we see some interesting results. On the Read Bandwidth side, the 533 MHz systems, despite having the same theoretical peak bandwidth, actually deliver slightly better performance. In this case, the higher clock speed and lower multiplier drives up the efficiency of the RDRAM system.
On the Write Bandwidth side, matters become even more interesting. The 533 MHz 850E chipset, paired with 40ns PC800 RDRAM, delivers substantially more bandwidth. Over 60% more write bandwidth, in fact. Our internal testing indicates that this is primarily due to the faster 40ns Core Access time of the RDRAMs used, while the 533 MHz bus speed itself accounts for a smaller percentage of the difference. What this actually translates into in terms of real world performance remains to be seen, however.
Clockspeed has virtually no bearing on the memory bandwidth scores, as the 2.53 GHz system turns in results similar to the 2.40 B GHz system.
http://media.hardwareanalysis.com/articles/small/10429.gif" alt="Hardware Analysis - 533 MHz FSB" border=0>
Cachemem can also be used to measure the latency of the memory subsystem. As expected, the faster FSB has no impact upon the latencies of the L1 and L2 caches on each CPU, as they turn in at 0.83ns and 7.5ns, respectively, for the parts operating at 2.40 GHz, and 0.79ns and 7.1ns for the 2.53 GHz part.
The faster bus does, however, serve to reduce the latency of the memory subsystem, if only slightly. In this case, when paired with the 850E chipset and PC800-40 RDRAM, the latency of the memory system as observed by the processor dropped by two cycles, from 38.3ns down to 37.5ns on the 2.40 GHz part. Our internal testing indicates that this slight decrease in latency is entirely due to the bus speed increase, and not the 40ns RDRAM (a system using a 400 MHz bus and 40ns RDRAM gave a latency of 92 cycles as well).
*To calculate latencies in a time-base, first calculate the Period of the processor by dividing 1 by its clock frequency, and multiply that Period by the number of clock cycles shown on the graph. For example, the 2.40 GHz Pentium 4's L2 latency is:
(1 / 2,400,000,000Hz) * 18 cycles = 0.0000000075 secs = 7.5ns.
Latencies are typically expressed in Nanoseconds. One nanosecond is equivalent to 1x10^-9 seconds. Given the Pentium 4's extremely low L1 latency, though, it may soon be more practical to represent such times in picoseconds (1x10^-12).