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  IDF, Centrino and Prescott 
  Feb 19, 2003, 04:00pm EST 
 
By: Sander Sassen

Welcome back as we bring you another update from the conference. Today is the second day, filled to the brim with mobile computing, Centrino, Pentium-M and the much touted convergence of computers and mobile devices. The Centrino mobile technology and the Pentium-M will actually be introduced at a variety of different price points, starting with the 900MHz Ultra Low Voltage version all the way up to the top-of-the-line 1.6GHz version in 100MHz increments. With the accompanying Intel 855 chipset family and the Intel Pro Wireless 2011 network connection the Pentium-M forms a compact and low-power basis for a high-performance notebook.

The architectural benefits of the Pentium-M for the mobile segment focus heavily around the SpeedStep technology, the SSE2 instructions and naturally the large 1MB L2-cache which, in combination with the 400MHz FSB, will give the Pentium-M similar or better performance than the Pentium 4-M. What’s a big benefit though is the fact that the battery life is much improved, with a 48Whr battery pack the 1.6GHz Pentium-M based notebook lasts about 315 minutes doing regular office tasks whereas a comparable 2.4GHz Pentium 4-M would last only 170 minutes.

Pentium-M Architecture


Fig 1. A slide from the Pentium-M presentation, previously codenamed ‘Banias’ and now known as Pentium-M.

The other topic that got much attention today is Prescott, the 90nm version of the Pentium 4. Besides the die-shrink Prescott will incorporate a lot of new features that’ll help boost performance and further increase clockspeed. Features that Intel disclosed during the Prescott briefing are a much improved branch predictor, 13 new SIMD extensions to the SSE2 set, La Grande support and lots of other tricks to reduce latencies and improved the execution efficiency. La Grande is actually a security feature at the hardware level which will or will not provide greater security for end users, depending on what direction the hardware and software developers choose to take it. The Prescott will be manufactured with strained silicon on a 7-layer low-K metal interconnect process, so Intel is positively not going towards SOI like AMD with their Athlon-64.

Prescott CPU Scaling


Fig 2. The relative performance increases we’ll see from moving to a 90nm process and the increase in cache sizes for Prescott.

So in summary the Prescott core is set to break new grounds for Intel with a 90nm strained silicon process, new architectural advances with multi-core processors, multi-threading capabilities and a host of new instructions meant to further up the performance for the Prescott processor. These new instructions include, among others, support for floating point to integer conversions (FISTTP), complex arithmetic (ADDSUBPD, ADDSUBPS, MOVDDUP, MOVSHDUP, MOVSLDUP), video encoding (LDDQU) and thread synchronization (MONITOR, MWAIT). Furthermore Intel disclosed plans to hit the 15-20GHz clockspeed mark by 2010 with the upcoming Prescott processor scaling upwards to 5GHz, thus keeping pace with Moore’s Law.

Sander Sassen.

Next update: IDF, Product Showcase and Racecars - Feb 20, 2003, 6:00 PM
http://www.hardwareanalysis.com/content/article/1597/


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