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  The next Pentium 4 processor, Prescott arrives 
  Feb 02, 2004, 07:30am EST 

Caching In

By: Dan Mepham

The use of the 90nm transistor allows Intel to construct much larger (in terms of the number of transistors) processors, while keeping the physical size small. When processors are manufactured, the yield rates on those processors are directly related to how large, physically, the processors are. A processor that is twice the size of another is essentially twice as likely to contain manufacturing impurities, and therefore will be subject to much lower yield rates.

Weíve seen this on a simple basis with respect to Intelís server products. Later versions of the Pentium III Xeon, for example, incorporated huge on-die caches that bumped the transistor count into the hundreds of millions, and resulted in a die size two to three times the size of a typical desktop processor at the time. These huge Xeons were difficult to manufacture, and came with a corresponding price premium.

The move to 90nm technology has allowed Intel to cram a comparatively huge amount of cache memory onto the Pentium 4 die. Prescott improves on the previous Northwood processor by boasting a huge 1MB L2 cache. Despite the larger cache, which helps to drive Prescottís transistor count to over 125 million, the processorís physical size remains manageable at only 112 square millimeters Ė roughly 50% smaller than Intelís first Willamette Pentium 4 with its tiny 256kB L2 cache.

In addition, Intel has also taken the opportunity to increase the size of the Pentium 4ís L1 cache as well. Prescottís L1 data cache is now doubled to 16kB, while the L1 instruction cache (or Execution Trace Cache) remains at 12k micro-ops. The Pentium 4 was initially designed with a small 8kB L1 data cache as a tradeoff in order to maximize the speed of the cache. Set-associativity of the L1 data cache has also increased from 4-way to 8-way.

Northwood Die     Prescott Die

Figs. 1 & 2 - Color-enhanced photos of Intel's Pentium 4 processor dies. On the left is the 130nm Northwood core; the 90nm Prescott core is on the right. Notice the larger L2 area on the Prescott die.

As you'll see later in the benchmarks, however, there are tradeoffs necessary in order to implement such a large cache.

1. Introduction
2. Caching In
3. Branching Off
4. Round 3, SSE Gets a Refresh
5. Intel's 2004 Roadmap, Sock-et to Me!
6. Incremental Improvements
7. Something Rotten in Santa Clara
8. Performance - Cache Latency
9. Performance - Cache Bandwidth
10. Performance - Cache Throughput
11. Performance - ScienceMark 2.0
12. Performance - Sandra & PCMark
13. Performance - PCMark & AquaMark
14. Performance - SPECviewperf
15. Summary
16. Appendix A - Benchmark Configuration

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