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  The next Pentium 4 processor, Prescott arrives 
  Feb 02, 2004, 07:30am EST 

Something Rotten in Santa Clara

By: Dan Mepham

Despite what seems to be a largely improved processor, and one that should easily outperform a Northwood-core Pentium 4 at equivalent clock speed, this is not the case. Further, there are some strong indications that there is something very seriously wrong with Intel’s 90nm process.

Firstly, Prescott was delayed. Earlier roadmaps showed Prescott arriving at the end of 2003, which clearly hasn't been the case. Secondly, Prescott’s pipeline has been deepened versus Northwood’s (probably related to the delays) from 20 stages up to a whopping 31 stages. More importantly, signs indicate that this wasn’t a previously planned change, and Intel seems much less inclined to discuss it than is typically the case when these types of changes are made. From a company that prides itself on adhering to its roadmaps religiously, and that typically talks about these changes openly, this is some rather alarming behavior.

Typically a process shrink like this would allow an almost instant boost in clockspeed. The last drop, from the 180nm Willamette down to the 130nm Northwood allowed an almost instant 20% boost in clockspeed, which worked its way up to over 60% as the process was refined. The final Northwood at 3.40GHz is 70% faster than the fastest Willamette as a result of the success of the 130nm process.

This time, on the other hand, the drop to 90nm seems not to be resulting in the usual improvements. So much so, in fact, that a rather last-minute change to the pipeline was necessary to produce decent yields at the promised speeds. The longer pipeline will lower Prescott’s IPC, and largely offset any gains as a result of the improvements discussed. See our benchmarks for direct comparison.

Some would no doubt argue that Intel is simply taking its time, and preparing for the future, as there's no imminent danger from AMD at the moment (which also seems to be having trouble with its 130nm strained silicon process - coincidence?). There may be some validity to that argument. Unfortunately at this point we can’t offer anything more than speculation. Intel’s public position is that everything is just fine, a 31-stage pipeline was all part of the plan, and it still promises 4GHz by year end. Yet its actions seem to indicate behind-the-scenes scrambling. Usually when there's this much whispering about problems, and such a tight-lipped reaction from the company, there's at least some truth to the speculation. We leave you to form your own conclusions.

1. Introduction
2. Caching In
3. Branching Off
4. Round 3, SSE Gets a Refresh
5. Intel's 2004 Roadmap, Sock-et to Me!
6. Incremental Improvements
7. Something Rotten in Santa Clara
8. Performance - Cache Latency
9. Performance - Cache Bandwidth
10. Performance - Cache Throughput
11. Performance - ScienceMark 2.0
12. Performance - Sandra & PCMark
13. Performance - PCMark & AquaMark
14. Performance - SPECviewperf
15. Summary
16. Appendix A - Benchmark Configuration

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