You say "Most code is executed from main memory...", but I've always understood that 9 out of 10 hits are satisfied from L1,L2 cache memory. Check this NG thread -
http://groups.google.com/groups?q=athlon+cache+bandwidth&h...garden.net

ok so with that your telling me that the P4 256 L1 and L2 cache is just a bunch of garbage untell they can fix it, somewhere in the hardware there is an issue that Intel did not address but it is fast that is without a dought, but the CPU throttling doesnt help either, what i wanted to know is if the CPU is only using a 32, 64, or a 128 bit regester then why did they make it 256 if the CPU isnt going to use the bandwith? and if the Bandwith is not the problem then does it have to do with the conversion to 256 bit regester?