Following reading this article, I am confident I have been able to solve a problem with a Win98se P3 system, which uses a VIA motherboard with VIA Apollo 694AS chip set and 1GHz P3 processor, 2 x 30GB hard disks, and an All-In-Wonder AGP card.
Connected with this via an Ethernet LAN I have a similar machine downstairs, identical except that it has a 733MHz processor.
A year ago, the upstairs machine became unstable though, since it coincided with a virus attack on both machines, I confused the problem with viruses. Though both needed a complete reformat of the main C-drive, I got the downstairs machine working fairly quickly. The upstairs machine, however, has continued to be unstable in extraordinary ways. For instance files saved to CD would prove to be corrupted, the system would report software violations on most occasions when used, Office WORD and ACCESS would sometimes claim files were unavailable to access, and on 2 separate occasions Windows reported the C drive as "non-DOS". This was confirmed by running FDISK, whence it was also discovered the second backup D-drive had also been made"non DOS". I tried changing hardware including memory and power supply. Each time there seemed to be an initial improvement but then the instability returned.
After reading the article about processor Vcore I downloaded the datasheet for my PGA370 socket P3 processor. Over 2 days of tests, I tried increasing the Vcore to the processor from 1.7V to 1.75V and then to 1.8V. (1.75 seemed best). These tests showed dramatic improvements to the stability of the system but I became concerned about running the processor at the higher than spec voltage.
To change the Vcore, I had used an undocumented section in the motherboard BIOS setup program and this section also included a mechanism to change the frequency of the processor internal DRAM bus clock. It occurred to me that, as an alternative to increasing the Vcore, I should be able to improve the shape of the data voltage pulses by reducing the clock frequency of the processor internal DRAM bus from 133MHz to 100MHz. thereby obtaining the same effect, i.e. increase the likelihood of the data voltage pulses reaching a readable threshold potential for the logic. Since doing this the system seems to have remained stable and has not crashed in 2 weeks of testing. The motherboard clock speed clock remains unchanged, being set to 133MHz by jumpers, the processor clock speed is 133MHz tied to the motherboard clock via the BIOS, processor DRAM clock is reduced to 100MHz, and the processor Vcore is set at the default 1.7 volts.
I would be grateful of any comments people might have as my electronic development days ceased in the early 1980sand before looking into this, I was unaware that modern processors have a different internal bus to the motherboard memory.