Dan,

I think your conclusions on the Cachemem results may be off target a touch.

Here's the quote in question:

"One interesting item to note here is that the performance of the 500FSB/266MEM platform is closer to that of the 500/333 than the 500/266. This indicates that the latency seen by Cachemem is more affected by Front Side Bus bandwidth than by memory bandwidth."

Going back to your mentioning that the 500FSB/266MEM platform is actually running at 500FSB/250MEM, I would submit that the added FSB bandwidth is not the only factor and may not even be the main factor in the difference. The 500FSB/250MEM is actually running in sync where if it was actually running at 500FB/266MEM, it would be running asynch. As we've seen with many other platforms, the memory bus running asynch to the FSB can incur significant penalties.

Good point. Observed latency is likely to decrease when using a synchronous setting, definitely.